1. Field of the Invention
The present invention relates to a design of very large scale integration (VLSI) for realizing an image data compression algorithm with hardware, and more particularly, to an apparatus and a method for performing mixed motion estimation based on a hierarchical search of an image data compression algorithm.
2. Description of the Related Art
In general, image signals are highly correlative with adjacent scenes. Motion estimation has been used in reducing redundant information of an image existing on time axis to increase image compression efficiency. A large number of calculations are necessary for this motion estimation. Also, algorithms and hardware for the calculations have been studied.
FIG. 1 is a block diagram of a motion estimation apparatus 10 based on a hierarchical search according to the prior art. A motion estimation algorithm based on a hierarchical search is disclosed in U.S. Pat. No. 5,706,059, entitled “MOTION ESTIMATION USING A HIERARCHICAL SEARCH”, Ran, Jan. 6, 1998. The circuit configuration of the motion estimation apparatus 10 as shown in FIG. 1 is the same as shown in FIG. 2 of U.S. Pat. No. 5,706,059.
Referring to FIG. 1, the motion estimation apparatus 10 includes first and second internal memories 11 and 12, a processing element unit 13, a comparator 14, and an address generator 15.
Describing each of blocks constituting the motion estimation apparatus 10, the first and second internal memories 11 and 12 receive a previous image data and a current image data, respectively, from external memories for a hierarchical search for motion estimation. The processing element unit 13 obtains the differences between absolute values of the previous image data and the current image data. The comparator 14 obtains the minimum motion vector based on the differences obtained from the processing element unit 13. The processing element unit 13 includes five processing elements 131 through 135 to obtain the differences in parallel. The processing element unit 13 has five search regions with respect to the five processing elements 131 through 135. The address generator 15 generates an address of a next stage after the comparator 14 obtains the minimum motion vector.
However, the motion estimation apparatus 10 is realized using additional memories. Thus, there are problems in that the area of the motion estimation apparatus 10 becomes large and power consumption increase. Also, since memories each have different structures, a large number of operations are necessary in motion estimation.